library verilog;
use verilog.vl_types.all;
entity fourplus2 is
    port(
        S1              : out    vl_logic;
        a1              : in     vl_logic;
        b1              : in     vl_logic;
        Ci_1            : in     vl_logic;
        S2              : out    vl_logic;
        a2              : in     vl_logic;
        b2              : in     vl_logic;
        S3              : out    vl_logic;
        a3              : in     vl_logic;
        b3              : in     vl_logic;
        S4              : out    vl_logic;
        a4              : in     vl_logic;
        b4              : in     vl_logic;
        CO_4            : out    vl_logic
    );
end fourplus2;
